1. Field of the Invention
The present invention generally relates to optical disk signal reproduction, and more particularly to a reproducing rate control apparatus for an optical disk in which data pieces and clock components for respective data pieces are recorded on the optical disk at a constant linear velocity.
2. Description of the Related Art
A CD-ROM (compact disc-read only memory) disk is a type of an optical disk. Similarly to an audio CD (compact disk), digital data signals are recorded on the CD-ROM disk by using an EFM (eight-to-fourteen modulation) method. That is, the CD-ROM disk is in such a data recording format that a length of a frame (which is a unit of data recorded thereon) is invariable regardless of whether the frame is located on an inner track of the disk or on an outer track of the disk.
In a CD-ROM reproducing system, a scanning of the CD-ROM disk is performed at a constant linear velocity by using an optical pickup when the disk is rotated, in order to reproduce a data signal from the CD-ROM disk at a constant bit rate. To perform the scanning of the disk, a rotating speed of a spindle motor which rotates the CD-ROM disk is controlled at the constant linear velocity, so that the rotating speed of the CD-ROM disk is varied in accordance with a position of the pickup in a radial direction of the CD-ROM disk.
FIG. 1 shows a conventional CD-ROM reproducing system 110. In this conventional CD-ROM reproducing system 110, a CD-ROM disk 21 (which will be called the disk 21) is rotated by a spindle motor 23. Digital signals are recorded on the disk 21 by using the EFM method, and the density of recorded data is constant in all areas of the disk 21.
In the conventional CD-ROM reproducing system 110, a self-clock frequency control operation is performed, which will be described below.
To reproduce data signals from the disk 21, a scanning of the disk 21 is performed by an optical pickup 24 (which will be called the pickup 24) in accordance with the CLV (constant linear velocity) method. The pickup 24 irradiates the disk 21 with a light ray, and reads data signals from a reflected ray from the disk 21. Data signals are reproduced from the disk 21 at a predetermined bit rate.
The disk 21 is rotated by the spindle motor 23 at a controlled rotating speed. The spindle motor control unit 40 generates a motor speed control signal to control a rotating speed (or a number of revolutions per minute) of the spindle motor 23. The scanning of the disk 21 is performed by the pickup 24 when the disk 21 is rotated at a reference-line rotating speed.
A pickup servo control unit 25 generates a focusing control signal to the pickup 24 based on a reproduce signal from the pickup 24, so that a focusing of the pickup 24 is performed. Also, the pickup servo control unit 25 generates a tracking control signal to the pickup 24 in accordance with a tracking command from a control CPU 45, to control a tracking of the pickup 24. Also, the pickup servo control unit 25 generates a seek control signal to the pickup 24 in accordance with a seek command from the control CPU 45, to control a seeking of the pickup 24. In the seeking operation, the pickup 24 is moved in a radial direction of the disk 21 to search for a desired track of the disk 21.
In a data reproducing mode, the pickup servo control unit 25 controls the tracking of the pickup 24 to the disk 21. In a seeking mode, the pickup servo control unit 25 controls the movement of the pickup 24 in the radial direction to a desired track of the disk 21.
When the seeking mode is performed, the control CPU 45 detects the amount of movement of the pickup 24 required to move it from the present track to the desired track for the seeking in accordance with a tracking error signal from the pickup servo control unit 25, and controls the movement of the pickup 24 from the present track to the desired track.
A waveform shaping unit 32 generates an EFM signal from the reproduction signal output from the pickup 24. The reproduction signal from the pickup 24 is amplified, and a waveform of the amplified signal is shaped. The EFM signal generated by the waveform shaping unit 32 is a digital reproduction signal derived from the reproduction signal from the pickup 24.
A synchronizing clock generating unit 33 generates a synchronizing clock pulse having a phase which is locked to a phase of the EFM signal output from the waveform shaping unit 32. The synchronizing clock pulse from the synchronizing clock generating unit 33 is supplied to various units of the CD-ROM reproducing system 110.
A self-clock frequency sweeping unit 46 supplies a frequency control signal to the synchronizing clock generating unit 33 when the synchronizing clock pulse from the synchronizing clock generating unit 33 is in an asynchronous state with the EFM signal. In the self-clock frequency sweeping unit 46, a sweeping of the self-clock pulse frequency in a triangular waveform within a lock range of frequencies from the synchronizing clock generating unit 33 is performed.
A synchronous-state detecting unit 34 inputs the EFM signal output from the waveform shaping unit 32 and the synchronizing clock pulse output from the synchronizing clock generating unit 33. The synchronous-state detecting unit 34 detects whether the synchronizing clock pulse is in a synchronous state. More specifically, it detects whether a synchronizing pattern (e.g., a frame synchronizing pattern "11T/11T", where T is a period of one bit) of the synchronizing clock pulse is in accordance with a synchronizing pattern of the EFM signal. When the synchronous state of the synchronizing clock pulse is detected, the synchronous-state detecting unit 34 outputs an ON signal indicative of the synchronous state of the synchronizing clock pulse. Otherwise the synchronous-state detecting unit 34 outputs an OFF signal indicative of the asynchronous state of the synchronizing clock pulse. The ON signal is supplied to each of the self-clock frequency sweeping unit 46, a spindle motor servo control unit 111, and a digital signal processing unit 35.
A system clock generating unit 58 generates a sequence of system clock pulses from a crystal oscillator. The crystal oscillator can provide system clock pulses with accurate frequency. The sequence of the system clock pulses from the system clock generating unit 58 are supplied to each of the signal processing unit 35 and the spindle motor servo control unit 40.
The spindle motor control unit 111 controls a rotating speed (or a number of revolutions per second) of the spindle motor 23 so that the scanning of the disk 21 is performed by the pickup 24 with a reference-line rotating speed, regardless of the movement of the pickup 24 in a radial direction of the disk 21.
The spindle motor control unit 111 generates a motor speed control signal to the spindle motor 23 when the synchronizing clock pulse from the unit 33 is in a synchronous state with the EFM signal from the unit 32 during the data reproducing mode. The rotating speed of the spindle motor 23 is controlled by the motor speed control signal from the spindle motor control unit 111, so that the disk 21 is rotated at the reference-line rotating speed.
In the spindle motor servo control unit 111, a frequency 1/M times (where M is an integer) the initial frequency of the synchronizing clock pulse from the unit 33 is compared with a frequency 1/N times (where N is an integer) the initial frequency of the system clock pulse from the system clock generating unit 58. In the spindle motor servo control unit 111, the phase of the synchronizing clock pulse having the 1/M times frequency is compared with the phase of the system clock pulse having the 1/N times frequency. The spindle motor servo control unit 111 supplies the motor speed control signal to the spindle motor 23.
When the synchronizing clock pulse from the unit 33 is in an asynchronous state with the EFM signal from the unit 32 after the end of the seeking mode, the spindle motor servo control unit 111 detects a greatest pulsewidth "11T" included in the EFM signal, and generates a pseudo-synchronizing clock pulse having a frequency inversely proportional to the pulsewidth "11T". The spindle motor servo control unit 111 generates a motor speed control signal by comparing the 1/M times frequency of the pseudo-synchronizing clock pulse with the 1/N times frequency of the system clock pulse. The spindle motor control unit 111 thus generates a motor speed control signal and supplies it to the spindle motor 23.
The integers M and N are preset to values that make the frequency of the synchronizing clock pulse and the frequency of the system clock pulse equal to each other when the frequency of the synchronizing clock pulse accords with a standard frequency.
The digital signal processing unit 35 includes a demodulator unit 51, a sub-code demodulator unit 52, a RAM (random access memory) 53, an error correcting unit 54, a bus 56 interconnecting the units 51, 52, 53 and 54, an address generator unit 55, and a timing control unit 113.
The demodulator unit 51 generates a demodulated data signal from the EFM signal in accordance with the synchronizing clock pulse when the synchronizing clock pulse is in the synchronous state with the EFM signal. The 14-bit data of the EFM signal is converted into the 8-bit data of the demodulated data signal. The demodulated data signal from the demodulator unit 51 is written to the RAM 53 via the bus 56. The sub-code demodulator unit 52 extracts a sub-code from the demodulated data signal from the demodulator unit 51 and supplies the sub-code to the control CPU 45.
The timing control unit 113 generates a first timing clock in accordance with a read reference clock pulse supplied from the system clock generating unit 58 and the synchronizing clock pulse supplied from the synchronizing clock generating unit 33, and supplies the first timing clock to each of the demodulator unit 51 and the address generator unit 55. The address generator unit 55 which is responsive to the first timing clock generates a first address signal. Thus, the demodulated data signal from the demodulator unit 52 is written to the RAM 53 at an address indicated by the first address signal in accordance with the first timing clock.
The timing control unit 113 generates a second timing clock, a third timing clock and a fourth timing clock in accordance with the read reference clock pulse supplied from the system clock generating unit 58. The timing control unit 113 supplies the second timing clock to each of the error correcting unit 54 and the address generator unit 55. The address generator unit 55 which is responsive to the second timing clock generates a second address signal. The demodulated data signal stored in the RAM 53 at an address indicated by the second address signal is read out in accordance with the second timing clock, and the demodulated data signal is supplied to the error correcting unit 54 via the bus 56.
The error correcting unit 54 performs an error correcting process for the demodulated data signal which was read from the RAM 53 in accordance with the second timing signal. The timing control unit 113 supplies the third timing clock to each of the error correcting unit 54 and the address generating unit 55. The address generator unit 55, responsive to the third timing clock, generates a third address signal. The demodulated data signal output from the error correcting unit 54 after the end of the error correcting process, is written to the RAM 53 at an address indicated by the third address signal in accordance with the third timing clock.
The timing control unit 113 supplies the fourth timing clock to each of a CD-ROM control unit 57 and the address generator unit 55. The address generator unit 55, responsive to the fourth timing clock, generates a fourth address signal. The demodulated data signal (which is error-corrected) stored in the RAM 53 at an address indicated by the fourth address signal is read out and supplied to the CD-ROM control unit 57 via the bus 56 in accordance with the fourth timing clock.
The demodulated data signal from the CD-ROM control unit 57 is transferred to a host system.
The above-described data flow in the digital signal processing unit 35 can be summarized as follows:
(1) the data signal transferred from the demodulator unit 51 to the RAM 53; PA0 (2) the data signal transferred from the RAM 53 to the error correcting unit 54; PA0 (3) the error-corrected data signal transferred from the error correcting unit 54 to the RAM 53; and PA0 (4) the error-corrected data signal transferred from the RAM 53 to the CD-ROM control unit 57.
The timing clock and the address signal used when transferring the data signal from the demodulator unit 51 to the RAM 53 are the first timing clock and the first address signal, which are generated in accordance with the synchronizing clock pulse.
The timing clock and the address signal used when transferring the data signal from the RAM 53 to the error correcting unit 54 are the second timing clock and the second address signal, which are generated in accordance with the read reference clock pulse.
The timing clock and the address signal used when transferring (or writing) the error-corrected data signal from the error correcting unit 54 to the RAM 53 are the third timing clock and the third address signal, which are generated in accordance with the read reference clock pulse.
The timing clock and the address signal used when transferring (or reading out) the error-corrected data signal from the RAM 53 to the CD-ROM control unit 57 are the fourth timing clock and the fourth address signal, which are generated in accordance with the read reference clock pulse.
The rate of the data signal supplied by the demodulator unit 51 is the same as the rate of the data signal read by the pickup 24 from the disk 21. Thus, the data signal supplied by the demodulator unit 51 includes a jitter component. To eliminate the jitter component, the data signal is temporarily written to the RAM 53 in accordance with the synchronizing clock pulse, and the data signal is read out from the RAM 53 in accordance with the read reference clock pulse.
The CD-ROM control unit 57 is connected to the digital signal processing unit 35. The error-corrected data signal from the RAM 53 is supplied to the CD-ROM control unit 57, and the fourth timing clock from the timing control unit 113 is supplied to the CD-ROM control unit 57. Thus, the error-corrected data signal from the RAM 53 is transferred to the CD-ROM control unit 57 in accordance with the fourth timing clock. The error-corrected data signal from the CD-ROM control unit 57 is supplied to the host computer.
The control CPU 45 controls the data reproducing operation and the seeking operation in accordance with a command signal supplied from the CR-ROM control unit 57. When the seeking operation is performed, the control CPU 45 generates a seeking command by using the address data in the sub-code extracted by the sub-code demodulator unit 52, and supplies it to the pickup servo control unit 25. Also, the control CPU 45 supplies an open-loop control command to the spindle motor control unit 111 so that an open-loop control operation of the spindle motor 23 is performed during the seeking operation.
In the above CD-ROM reproducing system 110, the self-clock frequency control operation is performed by using the self-clock frequency sweeping unit 46 to speed up the demodulation, the error correction and the data transferring operations of the digital signal processing unit 35.
However, the system clock pulse which is the read reference clock at which rate the data signal is read from or written to the RAM 53 is invariable in the above CD-ROM reproducing system 110. The frequencies of the second, third and fourth timing clocks which are generated in accordance with the read reference clock are constant. Therefore, the rate at which the data signal is read from or written to the RAM 53 is always constant even though a deviation of the synchronizing clock frequency from the standard frequency is great.
When a variable range of the self-clock frequency of the clock pulse supplied to the digital signal processing unit 35 is set to be wide, the difference between the synchronizing clock frequency and the standard frequency becomes great. If the variable range of the self-clock frequency is too wide, the quantity of data to be written to the RAM 53 may exceed the storage capacity of the RAM 53 when the rate of writing the demodulated data signal to the RAM 53 is high. Or, the quantity of data to be read from the RAM 53 may be greater than the quantity of data signals stored in the RAM 53 when the rate of writing the demodulated data signal to the RAM 53 is low.
Therefore, in the above CD-ROM reproducing system 110, it is difficult to set the variable range of the self-clock frequency to be wide in order to speed the digital signal processing. It is desirable to provide a CR-ROM reproducing system which performs the digital signal processing without causing the above-described problem even when the variable range of the self-clock frequency is wide.